University of Essex

CE339-6-SP-CO:
High Level Digital Design

The details

Year: 2024/25

Department: Computer Science and Electronic Engineering (School of)

Campus: Colchester Campus

Term: Spring

Level: Undergraduate: Level 6

Status: Current

Start date: Monday 13 January 2025

End date: Friday 21 March 2025

Credits: 15

Last updated: 24 October 2023

Requisites for this module

Pre-requisites: CE264

Co-requisites: (none)

Pre and / or co-requisites: (none)

Prohibited modules: (none)

Key module (requisite for): (none)

Key module for

BSC H60E Electronic System Engineering,
BSC H60ECO Electronic System Engineering,
BENGH641 Communications Engineering,
BENGHP41 Communications Engineering (Including Foundation Year),
BENGHPK1 Communications Engineering (Including Placement Year),
BENGHQ41 Communications Engineering (Including Year Abroad)

Module description

Digital systems are in virtually all devices we interact with: from consumer electronics, to biomedical applications and automotive industry. Digital technology is evolving so rapidly that engineers need rapid-prototyping software and hardware tools that allow them to explore and test an implementation before moving to the production.

In this module, learners will gain fundamental circuit design and verification skills by using an industry-standard hardware description language to program field-programmable gate arrays (FPGAs). The learning process is experience-oriented so that hands-on practice in designing embedded systems as well as theoretical background is acquired during the course.

Note: This module assumes that students are already familiar with combinatorial and sequential logic elements.

Module aims

The aim of this module is to study the application of digital systems to consumer electronics. With the rapid pace of change, digital design needs to be adaptive and fast to implement. Therefore, an industry standard hardware description language (HDL) will be used in this module to program field-programmable gate arrays (FPGAs).

Module learning outcomes

After completing this module, students will be expected to be able to:

1. Explain the process of automated digital system design using hardware description languages

2. Design and implement digital systems using hardware description languages

3. Test a HDL design using simulation and FPGA platform

4. Demonstrate an understanding of microprocessor design

Module information

Outline Syllabus

1. Introduction to behavioural, data flow, and structural modelling of VHDL.

2. Basic VHDL code structure and syntax.

3. Review of combinational and sequential logic. Definition of VHDL's concurrent and sequential modes.

4. Concurrent and sequential statements in VHDL.

5. Systematic review of VHDL's data types and data attributes. Signals and variables in VHDL.

6. Review of fundamental concepts related to finite state machines and the corresponding VHDL coding techniques.

7. Review and evaluation of hardware technologies (FPGAs, ASICs, microprocessors, microcontrollers, DSPs).

8. Introduction to the internal architecture and functioning of a microprocessor.

9. Importance of testing complex designs and validating the design prior to fabrication.

Learning and teaching methods

Lectures 18 hours & Labs 22 hours

Bibliography*

Pedroni, V.A. and Pedroni, V.A. (2010) Circuit design and simulation with VHDL. 2nd ed. Cambridge, MA: MIT Press. Available at: https://app.kortext.com/Shibboleth.sso/Login?entityID=https://idp0.essex.ac.uk/shibboleth&target=https://app.kortext.com/borrow/149745.
Kenneth L. Short (2008) VHDL for Engineers. Prentice Hall. Available at: https://ebookcentral.proquest.com/lib/universityofessex-ebooks/detail.action?docID=5174432.
'Learning FPGA development' (no date). Available at: https://www.linkedin.com/learning/learning-fpga-development/demo-system-for-the-intel-platform?u=51088249.

The above list is indicative of the essential reading for the course.
The library makes provision for all reading list items, with digital provision where possible, and these resources are shared between students.
Further reading can be obtained from this module's reading list.

Assessment items, weightings and deadlines

Coursework / exam	Description	Coursework weighting
Coursework	Progress Test 1	20%
Coursework	Progress Test 2	20%
Coursework	Assignment 1 - Project 1: HDL Introductory Design	20%
Coursework	Assignment 2 - Project 2: HDL Advanced Design	40%

Exam format definitions

Remote, open book: Your exam will take place remotely via an online learning platform. You may refer to any physical or electronic materials during the exam.
In-person, open book: Your exam will take place on campus under invigilation. You may refer to any physical materials such as paper study notes or a textbook during the exam. Electronic devices may not be used in the exam.
In-person, open book (restricted): The exam will take place on campus under invigilation. You may refer only to specific physical materials such as a named textbook during the exam. Permitted materials will be specified by your department. Electronic devices may not be used in the exam.
In-person, closed book: The exam will take place on campus under invigilation. You may not refer to any physical materials or electronic devices during the exam. There may be times when a paper dictionary, for example, may be permitted in an otherwise closed book exam. Any exceptions will be specified by your department.

Your department will provide further guidance before your exams.

Overall assessment

Coursework	Exam
100%	0%

Reassessment

Coursework	Exam
100%	0%

Module supervisor and teaching staff

Supervisor: Dr Wenqiang Yi, email: w.yi@essex.ac.uk.

Teaching staff: Dr Wenqiang Yi

Contact details: School Office, email: csee-schooloffice (non-Essex users should add @essex.ac.uk to create full e-mail address), Telephone 01206 872770

Availability

Available to incoming Essex Abroad / Exchange students: Yes

Available to Outside Option: No

Available to Audit: No

External examiner

Name: Dr Shadan Khan Khattak

Institution: Cardiff Metropolitan University

Academic role: Senior Lecturer

Resources

Teaching materials: Available via Moodle

Lecture recording:* Of 42 hours, 18 (42.9%) hours available to students:
24 hours not recorded due to service coverage or fault;
0 hours not recorded due to opt-out by lecturer(s).

Further information

Department website: Computer Science and Electronic Engineering (School of)

* Please note: due to differing publication schedules, items marked with an asterisk (*) base their information upon the previous academic year.

Disclaimer: The University makes every effort to ensure that this information on its Module Directory is accurate and up-to-date. Exceptionally it can be necessary to make changes, for example to programmes, modules, facilities or fees. Examples of such reasons might include a change of law or regulatory requirements, industrial action, lack of demand, departure of key personnel, change in government policy, or withdrawal/reduction of funding. Changes to modules may for example consist of variations to the content and method of delivery or assessment of modules and other services, to discontinue modules and other services and to merge or combine modules. The University will endeavour to keep such changes to a minimum, and will also keep students informed appropriately by updating our programme specifications and module directory.

The full Procedures, Rules and Regulations of the University governing how it operates are set out in the Charter, Statutes and Ordinances and in the University Regulations, Policy and Procedures.

Module Directory

CE339-6-SP-CO:High Level Digital Design