High Level Logic Design

The details
Computer Science and Electronic Engineering (School of)
Colchester Campus
Postgraduate: Level 7
Monday 13 January 2020
Friday 20 March 2020
15 January 2020


Requisites for this module



Key module for

MSC H61212 Computer Engineering

Module description

Digital systems are in virtually all devices we interact with: from consumer electronics, to biomedical applications and automotive industry. Digital technology is evolving so rapidly that engineers need rapid-prototyping software and hardware tools that allow them to explore and test an implementation before moving to the production.

In this module, learners will gain fundamental circuit design and verification skills by using an industry-standard hardware description language (VHDL) to program field-programmable gate arrays (FPGAs). The learning process is experience-oriented so that hands-on practice in designing embedded systems as well as theoretical background is acquired during the course.

Note: This module assumes that students are already familiar with combinatorial and sequential logic elements.

Module aims

The aim of this module is to study the application of digital systems to consumer electronics. With the rapid pace of change, digital design needs to be adaptive and fast to implement. Therefore VHDL, an industry standard hardware description language will be used in this module to program field-programmable gate arrays (FPGAs).

Module learning outcomes

After completing this module, students will be expected to be able to:

1. explain the process of automated digital system design using hardware description languages

2. design and implement digital systems using VHDL

3. test a VHDL design using simulation and FPGA platform

4. demonstrate an understanding of microprocessor design

Module information

Outline Syllabus

Introduction to behavioural, data flow, and structural modelling of VHDL.

Basic VHDL code structure and syntax.

Review of combinational and sequential logic. Definition of VHDL's concurrent and sequential modes.

Concurrent and sequential statements in VHDL.

Systematic review of VHDL's data types and data attributes. Signals and variables in VHDL.

Review of fundamental concepts related to finite state machines and the corresponding VHDL coding techniques.

Review and evaluation of hardware technologies (FPGAs, ASICs, microprocessors, microcontrollers, DSPs).

Introduction to the internal architecture and functioning of a microprocessor.

Importance of testing complex designs and validating the design prior to fabrication.

Learning and teaching methods

Labs and Lectures


  • Pedroni, Volnei A. (c2010) Circuit design and simulation with VHDL, Cambridge, MA: MIT Press.

The above list is indicative of the essential reading for the course. The library makes provision for all reading list items, with digital provision where possible, and these resources are shared between students. Further reading can be obtained from this module's reading list.

Assessment items, weightings and deadlines

Coursework / exam Description Deadline Weighting
Coursework   Progress Test 1 - Week 21    20% 
Coursework   Progress Test 2 - week 24    20% 
Coursework   Assignment 1   14/02/2020  20% 
Coursework   Assignment 2   27/03/2020  40% 

Overall assessment

Coursework Exam
100% 0%


Coursework Exam
100% 0%
Module supervisor and teaching staff
Dr Xiaojun Zhai, email: xzhai@essex.ac.uk.
Dr Luca Citi
School Office, e-mail csee-schooloffice (non-Essex users should add @essex.ac.uk to create full e-mail address), Telephone 01206 872770.



External examiner

Dr Rong Qu
The University of Nottingham
Associate Professor
Dr Marios Angelopoulos
Bournemouth University
Principal Academic
Available via Moodle
Of 42 hours, 18 (42.9%) hours available to students:
24 hours not recorded due to service coverage or fault;
0 hours not recorded due to opt-out by lecturer(s).


Further information

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