High Level Digital Design

The details
Computer Science and Electronic Engineering (School of)
Colchester Campus
Undergraduate: Level 6
Monday 15 January 2024
Friday 22 March 2024
24 October 2023


Requisites for this module



Key module for

BSC H60E Electronic System Engineering,
BSC H60ECO Electronic System Engineering

Module description

Digital systems are in virtually all devices we interact with: from consumer electronics, to biomedical applications and automotive industry. Digital technology is evolving so rapidly that engineers need rapid-prototyping software and hardware tools that allow them to explore and test an implementation before moving to the production.

In this module, learners will gain fundamental circuit design and verification skills by using an industry-standard hardware description language to program field-programmable gate arrays (FPGAs). The learning process is experience-oriented so that hands-on practice in designing embedded systems as well as theoretical background is acquired during the course.

Note: This module assumes that students are already familiar with combinatorial and sequential logic elements.

Module aims

The aim of this module is to study the application of digital systems to consumer electronics. With the rapid pace of change, digital design needs to be adaptive and fast to implement. Therefore, an industry standard hardware description language (HDL) will be used in this module to program field-programmable gate arrays (FPGAs).

Module learning outcomes

After completing this module, students will be expected to be able to:

1. Explain the process of automated digital system design using hardware description languages

2. Design and implement digital systems using hardware description languages

3. Test a HDL design using simulation and FPGA platform

4. Demonstrate an understanding of microprocessor design

Module information

Outline Syllabus

1. Introduction to behavioural, data flow, and structural modelling of VHDL.

2. Basic VHDL code structure and syntax.

3. Review of combinational and sequential logic. Definition of VHDL's concurrent and sequential modes.

4. Concurrent and sequential statements in VHDL.

5. Systematic review of VHDL's data types and data attributes. Signals and variables in VHDL.

6. Review of fundamental concepts related to finite state machines and the corresponding VHDL coding techniques.

7. Review and evaluation of hardware technologies (FPGAs, ASICs, microprocessors, microcontrollers, DSPs).

8. Introduction to the internal architecture and functioning of a microprocessor.

9. Importance of testing complex designs and validating the design prior to fabrication.

Learning and teaching methods

Lectures 18 hours & Labs 22 hours


The above list is indicative of the essential reading for the course.
The library makes provision for all reading list items, with digital provision where possible, and these resources are shared between students.
Further reading can be obtained from this module's reading list.

Assessment items, weightings and deadlines

Coursework / exam Description Deadline Coursework weighting
Coursework   Progress Test 1     20% 
Coursework   Progress Test 2     20% 
Coursework   Assignment 1 - Project 1: HDL Introductory Design     20% 
Coursework   Assignment 2 - Project 2: HDL Advanced Design    40% 

Exam format definitions

  • Remote, open book: Your exam will take place remotely via an online learning platform. You may refer to any physical or electronic materials during the exam.
  • In-person, open book: Your exam will take place on campus under invigilation. You may refer to any physical materials such as paper study notes or a textbook during the exam. Electronic devices may not be used in the exam.
  • In-person, open book (restricted): The exam will take place on campus under invigilation. You may refer only to specific physical materials such as a named textbook during the exam. Permitted materials will be specified by your department. Electronic devices may not be used in the exam.
  • In-person, closed book: The exam will take place on campus under invigilation. You may not refer to any physical materials or electronic devices during the exam. There may be times when a paper dictionary, for example, may be permitted in an otherwise closed book exam. Any exceptions will be specified by your department.

Your department will provide further guidance before your exams.

Overall assessment

Coursework Exam
100% 0%


Coursework Exam
100% 0%
Module supervisor and teaching staff
Dr Wenqiang Yi, email: w.yi@essex.ac.uk.
Dr Wenqiang Yi
School Office, email: csee-schooloffice (non-Essex users should add @essex.ac.uk to create full e-mail address), Telephone 01206 872770



External examiner

Dr Shadan Khan Khattak
Cardiff Metropolitan University
Senior Lecturer
Available via Moodle
Of 148 hours, 18 (12.2%) hours available to students:
128 hours not recorded due to service coverage or fault;
2 hours not recorded due to opt-out by lecturer(s), module, or event type.


Further information

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