CE339-6-SP-CO:
High Level Digital Design

The details
2020/21
Computer Science and Electronic Engineering (School of)
Colchester Campus
Spring
Undergraduate: Level 6
Current
Sunday 17 January 2021
Friday 26 March 2021
15
29 July 2020

 

Requisites for this module
CE264
(none)
(none)
(none)

 

CE869

Key module for

BSC H60E Electronic System Engineering,
BSC H60ECO Electronic System Engineering,
BSC H737 Mechatronics

Module description

Digital systems are in virtually all devices we interact with: from consumer electronics, to biomedical applications and automotive industry. Digital technology is evolving so rapidly that engineers need rapid-prototyping software and hardware tools that allow them to explore and test an implementation before moving to the production.

In this module, learners will gain fundamental circuit design and verification skills by using an industry-standard hardware description language (VHDL) to program field-programmable gate arrays (FPGAs). The learning process is experience-oriented so that hands-on practice in designing embedded systems as well as theoretical background is acquired during the course.

Note: This module assumes that students are already familiar with combinatorial and sequential logic elements.

Module aims

The aim of this module is to study the application of digital systems to consumer electronics. With the rapid pace of change, digital design needs to be adaptive and fast to implement. Therefore VHDL, an industry standard hardware description language will be used in this module to program field-programmable gate arrays (FPGAs).

Module learning outcomes

After completing this module, students will be expected to be able to:

1. explain the process of automated digital system design using hardware description languages

2. design and implement digital systems using VHDL

3. test a VHDL design using simulation and FPGA platform

4. demonstrate an understanding of microprocessor design

Module information

Outline Syllabus

1. Introduction to behavioural, data flow, and structural modelling of VHDL.

2. Basic VHDL code structure and syntax.

3. Review of combinational and sequential logic. Definition of VHDL's concurrent and sequential modes.

4. Concurrent and sequential statements in VHDL.

5. Systematic review of VHDL's data types and data attributes. Signals and variables in VHDL.

6. Review of fundamental concepts related to finite state machines and the corresponding VHDL coding techniques.

7. Review and evaluation of hardware technologies (FPGAs, ASICs, microprocessors, microcontrollers, DSPs).

8. Introduction to the internal architecture and functioning of a microprocessor.

9. Importance of testing complex designs and validating the design prior to fabrication.

Learning and teaching methods

Lectures 18 hours & Labs 22 hours

Bibliography*

  • Pedroni, Volnei A. (c2010) Circuit design and simulation with VHDL, Cambridge, MA: MIT Press.

The above list is indicative of the essential reading for the course. The library makes provision for all reading list items, with digital provision where possible, and these resources are shared between students. Further reading can be obtained from this module's reading list.

Assessment items, weightings and deadlines

Coursework / exam Description Deadline Weighting
Coursework   Assignment 1 - Project 1: VHDL Introductory Design     20% 
Coursework   Assignment 2 - Project 2: FPGA-based game    40% 
Practical   Progress Test 1 - Week 21    20% 
Practical   Progress Test 2 - Week 24    20% 

Overall assessment

Coursework Exam
100% 0%

Reassessment

Coursework Exam
100% 0%
Module supervisor and teaching staff
Dr Xiaojun Zhai, email: xzhai@essex.ac.uk.
Dr Xiaojun Zhai, Dr Liang Hu
CSEE School Office, email: csee-schooloffice (non-Essex users should add @essex.ac.uk to create full e-mail address), Telephone 01206 872770mail address), Telephone 01206 872770

 

Availability
Yes
No
No

External examiner

Dr Robert John Watson
University of Bath
Senior Lecturer
Resources
Available via Moodle
Of 42 hours, 18 (42.9%) hours available to students:
24 hours not recorded due to service coverage or fault;
0 hours not recorded due to opt-out by lecturer(s).

 

Further information

* Please note: due to differing publication schedules, items marked with an asterisk (*) base their information upon the previous academic year.

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