CE162-4-AP-NW:
Digital Electronic Systems
2019/20
Computer Science and Electronic Engineering (School of)
Northwest University
Autumn & Spring
Undergraduate: Level 4
Current
Thursday 03 October 2019
Friday 20 March 2020
15
15 May 2019
Requisites for this module
(none)
(none)
(none)
(none)
(none)
BSC H60E Electronic System Engineering
This module will examine how data are represented within digital systems, including floating point, 'text' and 'data' files, and how the conversions between internal and human-readable forms are performed. The design and applications of higher-level logic elements such as counters, registers and multiplexers are discussed, as well as the more general concept of the finite state machine and its design. Transmission of digital data between systems is introduced by examination of the RS232 protocol.
This module aims to develop the fundamental concepts introduced in the module, CE161, Digital Systems Architecture. The majority of the information in the world is in analogue format. Fundamental decisions are made as to how such sources should be represented in the digital domain.
After completing this module, students will be expected to be able to:
1. demonstrate an understanding of number systems, and conversion methods between number bases, including fixed and floating-point binary.
2. design digital circuits incorporating higher-level logic elements such as counters, registers and multiplexers.
3. perform forensic byte-level interpretation of data file contents using standard tools.
4. describe and implement a serial data transmission system.
5. select appropriate system parameters for digital representation of analogue signals.
6. be aware of methods to perform simple manipulations of digital image and audio data.
Outline Syllabus
Revision of binary number representation and binary arithmetic.
Number conversions between arbitrary bases.
Representation of floating-point binary numbers and applications in digital systems; accuracy of numerical calculations.
Use of Karnaugh map techniques in logic design, including variable-entered map logic design.
Sequential logic: Asynchronous and synchronous counters; finite state machines and their design; sequence detectors.
Asynchronous serial data transmission.
Analogue to digital and digital to analogue conversion techniques.
Sampling in theory (Nyquist's theorem) and in practice (sample and hold circuits). Quantization and quantization accuracy.
Frequency spectra and frequency domain representation of sampled data. Fourier series.
Data compression concepts.
Lectures and Laboratories
This module does not appear to have any essential texts. To see non-essential items, please refer to the module's reading list.
Assessment items, weightings and deadlines
| Coursework / exam |
Description |
Deadline |
Coursework weighting |
| Coursework |
Progress Test |
|
25% |
| Coursework |
Assignment 1 - Intro to Computer Aided Design for Digital and Analogue |
|
12.5% |
| Coursework |
Assignment 2 - CAD Digital Design and Report |
|
62.5% |
| Exam |
Main exam: 120 minutes during Summer (Main Period)
|
Exam format definitions
- Remote, open book: Your exam will take place remotely via an online learning platform. You may refer to any physical or electronic materials during the exam.
- In-person, open book: Your exam will take place on campus under invigilation. You may refer to any physical materials such as paper study notes or a textbook during the exam. Electronic devices may not be used in the exam.
- In-person, open book (restricted): The exam will take place on campus under invigilation. You may refer only to specific physical materials such as a named textbook during the exam. Permitted materials will be specified by your department. Electronic devices may not be used in the exam.
- In-person, closed book: The exam will take place on campus under invigilation. You may not refer to any physical materials or electronic devices during the exam. There may be times when a paper dictionary,
for example, may be permitted in an otherwise closed book exam. Any exceptions will be specified by your department.
Your department will provide further guidance before your exams.
Overall assessment
Reassessment
Module supervisor and teaching staff
Dr Ian Daly, email: i.daly@essex.ac.uk.
Dr Ian Daly
School Office, email: csee-schooloffice (non-Essex users should add @essex.ac.uk to create full e-mail address), Telephone 01206 872770
No
No
No
Dr Xu Wang
Heriot-Watt University
Associate Professor
Available via Moodle
No lecture recording information available for this module.
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